A dynamic random access memory (DRAM) is a type of semiconductor memory devices that senses and amplifies data stored in memory cells by means of a sense amplifier.
The sense amplifier, which is coupled to a pair of bitlines, senses data stored in a selected memory cell by detecting a difference in potential between the bitlines. One of the bitlines is connected to a capacitor in the selected memory cell. By detecting a difference between a voltage applied to this bitline by a charged stored in the capacitor, and a bitline precharge voltage applied to the other bitline, the sense amplifier detects data stored in the selected memory cell.
A sense amplifier may be exclusively assigned to one memory block. Alternatively, a sense amplifier may be shared by adjacent memory blocks, and configured to detect data in a memory cell of a selected memory block.
FIG. 1 shows an example of a memory device 100 constructed to include a shared sense amplifier. Referring to FIG. 1, there are several core circuits, such as bitline equalizing circuits 112 and 122, bitline isolation circuits 116 and 126, and a column selection circuit 140, which are arranged between a shared sense amplifier 130 and two adjacent memory blocks 110 and 120.
Each of the bitline equalizing circuits 112 and 122 provides a precharge voltage VBL to bitline pairs BL/BLB in first and second memory blocks 110 and 120 before the sense amplifier 130 senses a potential difference between the bitlines BL and BLB in one of these pairs. The first bitline isolation circuit 116 turns on and, thereby, electrically connects the bitline pair BL/BLB of the first memory block 110 with the sense amplifier 130, when the data of the memory cell in the first memory block 110 is to be sensed. At this time, the second bitline isolation circuit 126 turns off and thereby electrically disconnects the sense amplifier 130 with the bitline pair BL/BLB of the second memory block 120.
Alternatively, when the second bitline isolation circuit 126 operates to electrically connect the bitline pair BL/BLB of the second memory block 120 to the sense amplifier 130, the bitline pair BL/BLB of the first memory block 110 and the sense amplifier 130 are electrically disconnected via the first bitline isolation circuit 116.
The column selection circuit 140 transfers the data, which is amplified by the sense amplifier 130 from the selected one of the first and second memory blocks 110 and 120, to data input/output lines IO and IOB.
In the shared sense amplifier structure, a procedure whereby data of the memory cell MC0 of the first memory block 110 is sensed, followed by data in the memory cell MC1 of the second memory block 120 being sensed, is described below.
When first and second bitline equalizing signals PEQi and PEQj are set to high levels corresponding to an external voltage VEXT, the bitlines BL and BLB are pre-charged with the bitline precharge voltage VBL.
Thereafter, in order to sense the memory cell MC0 of the first memory block 110, the first bitline equalizing signal PEQi is set to a low level corresponding to a ground voltage (or a substrate voltage) VSS and the first bitline isolation signal PISOi is set to a high level corresponding to a boosting voltage VPP. A wordline WLn−1 of the memory cell MC0 is also set to the boosting voltage VPP. As a result, the data of the memory cell MC0 is transferred to the sense amplifier 130 as a result of the charge in the memory cell's MC0 capacitor being applied to the bitline BL.
On the other hand, to sense the data in memory cell MC1 of the second memory block 120, the second bitline equalizing signal PEQj is set to a low level corresponding to the voltage of VSS, while a wordline WL1 is driven with the boosting voltage VPP and the second bitline isolation signal PISOj is set to a high level of VPP. Then, the data of the memory cell MC1 is transferred to the sense amplifier 130 as a result of the memory cell's MC1 capacitor applying its charge to the bitline BL. In the meantime, the first bitline equalizing signal PEQi is set to a high level of VEXT, so that the bitlines BL and BLB of the first memory block 110 are pre-charged to the bitline precharge voltage VBL.
The above-described operation are further illustrated with reference to FIG. 2. Specifically, FIG. 2 illustrates the voltage levels of the bitline isolation signals PISOi and PISOj, the first bitline equalizing signal PEQi, and wordline signal WL as a first memory cell MC0 in the first memory bock 110 is selected. As shown in FIG. 2, the bitline isolation signals PISOi and PISOj each has a voltage level corresponding to an internal voltage VINT of the semiconductor memory device 100 as the bitlines BL and BLB of the first memory block 110 are being pre-charged. When the first memory block 110 is selected, the first bitline isolation signal PISOi is set to a high voltage level of VPP, while the second bitline isolation signal PISOj goes to a low voltage level of VSS.
At this time, the first bitline equalizing signal PEQi transitions from the high level of VEXT to the low-level of VSS. Thereafter, the wordline signal is set from the low-level of VSS to its high voltage level of VPP as data in memory cell MC0 is being sensed.
After the data is sensed, the wordline signal WL returns to VSS, and the first bitline equalizing signal PEQi is set to high (VEXT) to pre-charge the bitline pair BL/BLB. Thus, the bitline isolation signals PISOi and PISOj return to the level of internal voltage VINT.
By changing the first bitline equalizing signal PEQi from the low VSS to the high VEXT, the bitlines BL and BLB are pre-charged with the bitline precharge voltage VBL. The speed at which the bitlines BL and BLB are pre-charged with the bitline precharge voltage VBL is dependent on the gate-source voltages VGS of first and second equalizing transistors 113 and 114.
When the DRAM device 100 is harmonized with a low-voltage environment, the gate-source voltages VGS of the first and second equalizing transistors 113 and 114 is settled at about 0.5V when the internal voltage VINT is lowered to 1.0V. This is in accordance with the external voltage VEXT decreasing to 1.0V and the bitline precharge voltage VBL is established at half of the internal voltage VINT, i.e., 0.5V.
To pre-charge the bitline pairs BL/BLB of the first and second memory blocks 110 and 120, the bitline equalizing signals PEQi and PEQj should have voltages higher than the threshold voltages of the first and second equalizing transistors 113 and 114, respectively. However, in the low-voltage operating condition, if these threshold voltages are higher than 0.5V, the bitlines BL and BLB may not be pre-charged because the first and second equalizing transistors 113 and 114 are not turned on. In such a situation, the bitline equalizing signals PEQi and PEQj applied to the gates of the first and second transistors 113 and 114 should be set at a voltage level higher than the external voltage VEXT in order to pre-charge the bitline pairs BL/BLB.
Also, when the DRAM is situated in a standby mode under low-voltage operating conditions, the bitlines BL and BLB coupled to the sense amplifier 130 are pre-charged with the bitline precharge voltage VBL through the first and second bitline isolation circuits 116 and 126, respectively. Thus, the voltage levels of the first and second equalizing signals PEQi and PEQj should have voltage levels that exceed the bitline precharge voltage VBL at least by an amount equal to the threshold voltages of the equalizing transistors 113 and 114. Namely, to ensure that the equalizing signals PEQi and PEQj operate normally, their voltage levels should be at least equal to VBL+Vth (i.e., VINT/2+Vth=VEXT/2+Vth).
Therefore, it would be advantageous under the low-voltage operating condition for the bitline equalizing signals PEQi and PEQj to be bootstrapped up to voltage levels that are higher than the external voltage VEXT, by means of a pumping operation. However, such a voltage pumping inevitably causes current consumption even though the DRAM is designed to be operable in the low-voltage operational environment.